This document outlines the UEFI configuration menus and settings for the OnLogic Axial AC101 Edge Server. Within this document, the terms “BIOS” and “UEFI” are often used interchangeably to describe the firmware interface used to start up a system. UEFI is a more advanced firmware interface that provides similar functionality to legacy BIOS firmware. UEFI offers a more flexible and feature-rich environment for controlling hardware and boot processes. It is designed to work with larger hard drives and newer hardware features, such as 64-bit processors, Secure Boot, and virtualization. The Axial AC101 Edge Server utilizes modern UEFI firmware for enhanced functionality to enable the most recent technologies.
Note: Actual descriptive text may vary in UEFI menus. Screenshots as they appear in this user manual are for references only. Actual images may vary depending on firmware version.
To enter the UEFI Setup menu, press the or button on a keyboard while the system is powering on.
Once you enter the UEFI SETUP UTILITY, the Main screen will appear and display the system overview. The Main screen provides system overview information and allows you to set the system time and date.
Enter this item to view the motherboard information.
Enter this item to view the processor information.
Enter this item to view the memory information.
This option will make the CPU run at higher Vcores by default. Adjust this option if your CPU is not stable at default settings. A higher level will provide higher Vcore.
Type a profile name and press enter to save your settings as user default.
Load previously saved user defaults.
This feature allows you to save the current UEFI settings as a user profile to disk.
You can load a previously saved profile from the disk.
Allows users to browse the CPU Turbo Ratio Information.
The CPU speed is determined by the CPU P-Core Ratio multiplied by the BCLK. Increasing the CPU P-Core Ratio will increase the internal CPU clock speed without affecting the clock speed of other components.
AVX2 Ratio Offset specifies a negative offset from the CPU Ratio for AVX workloads. AVX is a more stressful workload that lowers the AVX ratio to ensure the maximum possible ratio for SSE workloads.
The E-Core speed is determined by the E-Core Ratio multiplied by the BCLK. Increasing the E-Core Ratio will increase the internal E-Core clock speed without affecting the clock speed of other components.
The CPU Internal Bus Speed Ratio. The maximum should be the same as the CPU Ratio.
Configure the frequency of the integrated GPU in MHz.
Enable/Disable CPU Flex Ratio Programming. Flex Ratio can lower maximum non-turbo, especially for CPUs without turbo function.
The CPU speed is determined by the CPU Ratio multiplied by the BCLK. Increasing the BCLK will increase the internal CPU clock speed but also affect the clock speed of other components.
Configure the PEG/DMI Frequency setting.
Configure the BCLK Advanced setting.
Configure the BCLK Spread Spectrum Mode setting.
After raising BCLK, BIOS adds a delay time (ms) for stability.
BCLK Aware Adaptive Voltage enable/disable. When enabled, pcode will be aware of the BCLK frequency when calculating the CPU V/F curves. This is ideal for BCLK OC to avoid high voltage overrides.
Select the performance state that the BIOS will set before OS handoff. Max Battery mode will set CPU ratio as xB till OS handoff. This option is suggested for BCLK overclocking.
Disable Ring to Core Ratio Offset so the ring and core can run at the same frequency.
Configure SA PLL Frequency.
BCLK TSC HW Fixup disabled during TSC copy from PMA to APIC.
Nominal is good for normal core ratio overclocking. Elevated and Extremely Elevated are good for high BCLK OC.
Intel SpeedStep technology allows processors to switch between multiple frequencies and voltage points for better power saving and heat dissipation. CPU turbo ratio can be fixed when Intel SpeedStep Technology is set to Disabled and Intel Turbo Boost Technology is set to Enabled.
Intel Turbo Boost Technology enables the processor to run above its base operating frequency when the operating system requests the highest performance state.
Enable/Disable Intel Speed Shift Technology support. Enabling this will expose the CPPC v2 interface to allow for hardware controlled P-States. For the best support of Intel Turbo Boost Max Technology 3.0 (ITBMT 3.0), enable Intel Speed Shift Technology. If your CPU does not support ITBMT 3.0, the option will be grayed out.
Enable/Disable Intel Turbo Boost Technology 3.0 (ITBMT 3.0) support. Disabling this will report the maximum ratio of the slowest core in the _CPC object. Processors supporting the ITBMT 3.0 feature contain at least one processor core whose maximum ratio is higher than the others.
This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
Enter this item to view TVB information.
Set CPU Tj Max to adjust TCC Target Temperature. It supports TjMax in the range of 62 to 115 degrees Celsius.
Enable Dual Tau Boost feature for 35W/65W/125W CPU to achieve performance boost with additional PL1 greater than TDP for limited durations.
Enable/Disable Load Intel Base Power Limit Settings. When enabled, the power limit and current limit will use Intel Base Power Limit Settings.
Configure Package Power Limit 1 in watts. When the limit is exceeded, the CPU ratio will be lowered after a period of time. A lower limit can protect the CPU and save power, while a higher limit may improve performance.
Configure the period of time until the CPU ratio is lowered when the Long Duration Power Limit is exceeded.
Configure Package Power Limit 2 in watts. When the limit is exceeded, the CPU ratio will be lowered immediately. A lower limit can protect the CPU and save power, while a higher limit may improve performance.
To unlock the voltage regulator current limit completely, you can set this option to Enabled.
Configure the Voltage Regulator Current Limit. This value represents the Maximum instantaneous current allowed at any given time.
To unlock the voltage regulator current limit completely, you can set this option to Enabled.
Configure the Voltage Regulator Current Limit. This value represents the Maximum instantaneous current allowed at any given time.
Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile (XMP) for DDR modules.
IMPORTANT NOTE: Modification of DRAM Timing settings should only be done by experts. Only the default (Auto) settings are tested and validated by OnLogic. Improper configuration may impact system functionality and/or stability.
Load XMP Setting
Load XMP settings to overclock the DDR memory and perform beyond standard specifications.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
BCLK Frequency
The CPU speed is determined by the CPU Ratio multiplied by the BCLK. Increasing the BCLK will increase the internal CPU clock speed but also affect the clock speed of other components.
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data in response.
RAS# to CAS# Delay (tRCD)
The number of clock cycles required between the opening of a row of memory and accessing columns within it.
Row Precharge Time (tRP)
The number of clock cycles required between the issuing of the precharge command and opening the next row.
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the precharge command.
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can be issued.
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged.
Refresh Cycle Time2 (tRFC2)
The number of clocks from a Refresh command until the first Activate command to the same rank.
Refresh Cycle Time per Bank (tRFCpb)
The number of clocks that a per back Refresh command takes to complete.
RAS to RAS Delay (tRRD_L)
The number of clocks between two rows activated in different banks of the same rank.
RAS to RAS Delay (tRRD_S)
The number of clocks between two rows activated in different banks of the same rank.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read command to the same internal bank.
Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read command to the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre-charge command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Third Timing tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR5 initiates a minimum of one refresh command internally once it enters Self-Refresh mode.
tRC
Configure the minimum active to active/Refresh Time.
Turn Around Timing Optimization
Auto is enabled in the general case.
TAT Training Value tRDRD_sg
Configure between module read to read delay.
tRDRD_dg
Configure between module read to read delay.
tRDRD_dr
Configure between module read to read delay.
tRDRD_dd
Configure between module read to read delay.
tRDWR_sg
Configure between module read to write delay.
tRDWR_dg
Configure between module read to write delay.
tRDWR_dr
Configure between module read to write delay.
tRDWR_dd
Configure between module read to write delay.
tWRRD_sg
Configure between module write to read delay.
tWRRD_dg
Configure between module write to read delay.
tWRRD_dr
Configure between module write to read delay.
tWRRD_dd
Configure between module write to read delay.
tWRWR_sg
Configure between module write to write delay.
tWRWR_dg
Configure between module write to write delay.
tWRWR_dr
Configure between module write to write delay.
tWRWR_dd
Configure between module write to write delay.
TAT Runtime Value tRDRD_sg
Minimum delay from read to read to the same bank group in tCK cycles.
tRDRD_dg
Minimum delay from read to read to different bank groups in tCK cycles.
tRDRD_dr
Minimum delay from read to read to the other rank in the same DIMM in tCK cycles.
tRDRD_dd
Minimum delay from read to read to the other DIMM in tCK cycles.
tRDWR_sg
Minimum delay from read to write to the same bank group in tCK cycles.
tRDWR_dg
Minimum delay from read to write to different bank groups in tCK cycles.
tRDWR_dr
Minimum delay from read to write to the other rank in the same DIMM in tCK cycles.
tRDWR_dd
Minimum delay from read to write to the other DIMM in tCK cycles.
tWRRD_sg
Minimum delay from write to read to the same bank group in tCK cycles.
tWRRD_dg
Minimum delay from write to read to different bank groups in tCK cycles.
tWRRD_dr
Minimum delay from write to read to the other rank in the same DIMM in tCK cycles.
tWRRD_dd
Minimum delay from write to read to the other DIMM in tCK cycles.
tWRWR_sg
Minimum delay from write to write in the same bank group in tCK cycles.
tWRWR_dg
Minimum delay from write to write to different bank groups in tCK cycles.
tWRWR_dr
Minimum delay from write to write to the other rank in the same DIMM in tCK cycle.
tWRWR_dd
Minimum delay from write to write to the other DIMM in tCK cycles.
Round Trip Timing Optimization
Auto is enabled in the general case.
Round Trip Level
Configure round trip level.
Initial RTL IO Delay Offset
Configure round trip latency IO delay initial offset.
Initial RTL FIF0 Delay Offset
Configure round trip latency FIF0 delay initial offset.
Initial RTL (MC0 C0 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC0 C1 A1/A2)
Configure round trip latency initial value.
Initial RTL (MC1 C0 B1/B2)
Configure round trip latency initial value.
Initial RTL (MC1 C1 B1/B2)
Configure round trip latency initial value.
RTL (MC0 C0 A1/A2)
Configure round trip latency.
RTL (MC0 C1 A1/A2)
Configure round trip latency.
RTL (MC1 C0 B1/B2)
Configure round trip latency.
RTL (MC1 C1 B1/B2)
Configure round trip latency.
Dimm ODT Training
ODT values will be optimized by Dimm On-Die Termination Training.
ODT WR (A1)
Configure the memory on die termination resistors WR.
ODT WR (A2)
Configure the memory on die termination resistors WR.
ODT WR (B1)
Configure the memory on die termination resistors WR.
ODT WR (B2)
Configure the memory on die termination resistors WR.
ODT NOM Rd (A1)
Configure the memory on die termination resistors NOM Rd.
ODT NOM Rd (A2)
Configure the memory on die termination resistors NOM Rd.
ODT NOM Rd (B1)
Configure the memory on die termination resistors NOM Rd.
ODT NOM Rd (B2)
Configure the memory on die termination resistors NOM Rd.
ODT PARK (A1)
Configure the memory on die termination resistors PARK.
ODT PARK (A2)
Configure the memory on die termination resistors PARK.
ODT PARK (B1)
Configure the memory on die termination resistors PARK.
ODT PARK (B2)
Configure the memory on die termination resistors PARK.
ODT PARK DQS (A1)
Configure the memory on die termination resistors PARK DQS.
ODT PARK DQS (A2)
Configure the memory on die termination resistors PARK DQS.
ODT PARK DQS (B1)
Configure the memory on die termination resistors PARK DQS.
ODT PARK DQS (B2)
Configure the memory on die termination resistors PARK DQS.
ODT CA (A1 Group A)
Configure the memory on die termination resistors ODT CA.
ODT CA (A2 Group A)
Configure the memory on die termination resistors ODT CA.
ODT CA (B1 Group A)
Configure the memory on die termination resistors ODT CA.
ODT CA (B2 Group A)
Configure the memory on die termination resistors ODT CA.
ODT CA (A1 Group B)
Configure the memory on die termination resistors ODT CA.
ODT CA (A2 Group B)
Configure the memory on die termination resistors ODT CA.
ODT CA (B1 Group B)
Configure the memory on die termination resistors ODT CA.
ODT CA (B2 Group B)
Configure the memory on die termination resistors ODT CA.
ODT CS (A1 Group A)
Configure the memory on die termination resistors ODT CS.
ODT CS (A2 Group A)
Configure the memory on die termination resistors ODT CS.
ODT CS (B1 Group A)
Configure the memory on die termination resistors ODT CS.
ODT CA (B2 Group A)
Configure the memory on die termination resistors ODT CS.
ODT CS (A1 Group B)
Configure the memory on die termination resistors ODT CS.
ODT CS (A2 Group B)
Configure the memory on die termination resistors ODT CS.
ODT CS (B1 Group B)
Configure the memory on die termination resistors ODT CS.
ODT CS (B2 Group B)
Configure the memory on die termination resistors ODT CS.
ODT CK (A1 Group A)
Configure the memory on die termination resistors ODT CK.
ODT CK (A2 Group A)
Configure the memory on die termination resistors ODT CK.
ODT CK (B1 Group A)
Configure the memory on die termination resistors ODT CK.
ODT CK (B2 Group A)
Configure the memory on die termination resistors ODT CK.
ODT CK (A1 Group B)
Configure the memory on die termination resistors ODT CK.
ODT CK (A2 Group B)
Configure the memory on die termination resistors ODT CK.
ODT CK (B1 Group B)
Configure the memory on die termination resistors ODT CK.
ODT CK (B2 Group B)
Configure the memory on die termination resistors ODT CK.
OnLogic Timing Optimization
Enable/Disable OnLogic Timing Optimization. When Enabled, the memory timing will use OnLogic optimized value.
OnLogic DRAM Frequency Optimization
Enable/Disable OnLogic DRAM Frequency Optimization. When Enabled, the DRAM Frequency will use OnLogic optimized procedure.
MRC Training Respond Time
Configure the MRC Training Respond Time.
Configure the realtime memory timings.
[Enabled] The system will allow performing realtime memory timing changes after MRC_DONE.
Reset for MRC Failed
Reset system after MRC training is failed.
IMPORTANT NOTE: Modification of Voltage settings should only be done by experts. Only the default (Auto) settings are tested and validated by OnLogic. Improper configuration may impact system functionality and/or stability.
Input voltage for the processor by the external voltage regulator.
CPU Core/Cache Load-Line Calibration helps prevent CPU Core/Cache voltage droop when the system is under heavy loading.
Configure CPU CORE/Cache Auto Phase.
Configure CPU CORE/Cache Over Current Protection.
Configure CPU CORE/Cache Over Voltage Protection.
Configure CPU CORE/Cache Under Voltage Protection.
Configure CPU CORE/Cache Over Temperature Protection.
Configure the voltage for the integrated GPU.
GT Load-Line Calibration helps prevent integrated GPU voltage droop when the system is under heavy load.
Configure CPU GT Over Current Protection.
Configure CPU GT Over Voltage Protection.
Configure CPU GT Under Voltage Protection.
Configure CPU GT Over Temperature Protection.
Input voltage for the processor by the external voltage regulator.
VCCIN_AUX Load-Line Calibration helps prevent VCCIN_AUX voltage droop when the system is under heavy loading.
Configure VCCIN_AUX Auto Phase.
Configure VCCIN_AUX Over Current Protection.
Configure VCCIN_AUX Over Voltage Protection.
Configure VCCIN_AUX OTP Mode.
Configure VCCIN_AUX OTP Temperature.
Configure the voltage for the VDD_CPU.
Configure the voltage for the +0.82V PCH.
Configure the voltage for the +1.05 PCH.
Configure the voltage for the +1.8V PROC.
Configure the voltage for the +1.05V PROC.
Choose separate to individually adjust DIMM PMIC.
Configure the memory VDD Voltage.
Configure the memory VDD Voltage Range.
Configure the memory VDDQ Voltage.
Configure the memory VDDQ Voltage Range.
Configure the memory VPP Voltage.
Configure the memory VDD Eventual Voltage.
Configure the memory VDDQ Eventual Voltage.
Configure the memory VPP Eventual Voltage.
Configure the PMIC Protection Unlock setting.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
PLL Voltage offset ranges from 0 to 15 bins, with each bin being 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will differ on each processor; the user must find the best bins for their own processor.
AVX2 Voltage Guardband Scale Factor
AVX2 Voltage Guardband Scale Factor controls the voltage guardband applied to AVX2 workloads. A value > 1.00 will increase the voltage guardband, and < 1.00 will decrease the voltage guardband.
The Advanced configuration screen allows for configuration of the following:
CPU Configuration
Chipset Configuration
PCH-FW Configuration
Storage Configuration
This item displays the P-Core Information.
This item displays the E-Core Information.
Intel Hyper Threading Technology allows multiple threads to run on each core, so that the overall performance on threaded software is improved.
The Pre-Core Hyper Threading feature allows you to disable Hyper Threading on specific cores.
Select the number of cores to enable in each processor package.
Select the number of E-Cores to enable in each processor package.
Enable CPU C States Support for power saving. It is recommended to keep C6 and C7 enabled for better power saving.
Enable Enhanced Halt State (C1E) for lower power consumption.
Enable C6 deep sleep state for lower power consumption.
Enable C7 deep sleep state for lower power consumption.
Enable CPU, PCIe, Memory, Graphics C State Support for power saving.
This item allows you to disable or enable the CFG Lock.
Enable/Disable moving of DRAM contents to PRM memory when CPU is in C6 state.
Enable CPU internal thermal control mechanisms to keep the CPU from overheating.
Enable/Disable the Intel AVX and AVX2 Instructions. This is applicable for Big Core only.
Enable/Disable the Intel AVX-512 (a.k.a. AVX3) Instructions. This is applicable for Performance Core only.
Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions, so that one computer system can function as multiple virtual systems.
Automatically prefetch data and code for the processor. Enable for better performance.
Automatically prefetch the subsequent cache line while retrieving the currently requested cache line. Enable for better performance.
When enabled, pressing the scroll lock key will toggle the Efficient cores between being parked when Scroll Lock LED is on and un-parked when LED is off.
To enable or Disable Onboard VGA.
To enable or Disable Onboard LAN.
To enable or Disable Onboard LAN.
Select to disable the integrated graphics when an external graphics card is installed. Select enable to keep the integrated graphics enabled at all times.
Configure the size of memory that is allocated to the integrated graphics processor when the system boots up.
Enable audio for the onboard digital outputs.
Use this option to enable or disable Resizable BAR support (only if the system supports 64 bit PCI decoding).
Intel® Virtualization Technology for Directed I/O helps your virtual machine monitor better utilize hardware by improving application compatibility and reliability, and providing additional levels of manageability, security, isolation, and I/O performance.
Switch the COUlink to PCIE/SATA.
Configure PCIE6 Slot Link Width.
Configure PCIE7/OCU4, PCIe6, M.2, PCIe4, OCU1, OCU2, OCU3 Link Speed.
Configure PCIE7/OCU4, PCIe6, M.2, PCIe4, OCU1, OCU2, OCU3 Hot Plug.
Configure PCIE7/OCU4, PCIe6, M.2, PCIe4, OCU1, OCU2, OCU3 Hot Plug.
Enable/disable Intel PTT in ME. Disable this option to use a discrete TPM Module.
Enable/disable the SATA controllers.
This item allows selection of Hybrid Storage Detection and Configuration Mode.
SATA Aggressive Link Power Management allows SATA devices to enter a low power state during periods of inactivity to save power. It is only supported by AHCI mode.
S.M.A.R.T stands for Self-Monitoring, Analysis, and Reporting Technology. It is a monitoring system for computer hard disk drives to detect and report on various indicators of reliability.
The NVMe Configuration screen displays the NVMe controller and Drive information.
Select disable for ACPI suspend type S1. It is recommended to select auto for ACPI S3 power saving.
Allow the system to be woken up by a PCIE device and enable wake on LAN.
Allow the system to be woken up by the real time clock alarm. Set it to By OS to let it be handled by your operating system.
Allow the system to be woken up by an USB keyboard or remote controller.
Allow the system to be woken up by an USB mouse.
This page displays the information of the USB controllers and USB devices.
Use this item to set parameters of COM.
Serial Port
Use this item to enable or disable the serial port (COM).
Change Settings
Use this item to select an optimal setting for a Super IO device.
Use this item to set parameters of SOL.
Serial Port
Use this item to enable or disable the SOL port.
Change Settings
Use this item to select an optimal setting for Super IO device.
Console Redirection
Use this option to enable or disable Console Redirection. If this item is set to Enabled, you can select a COM Port to be used for Console Redirection.
Console Redirection Settings
Use this option to configure Console Redirection Settings, and specify how your computer and the host computer to which you are connected exchange information.
Terminal Type
Use this item to select the preferred terminal emulation type for out-of-band management. It is recommended to select [VT-UTF8].
Bits Per Second
Use this item to select the serial port transmission speed. The speed used in the host computer and the client computer must be the same. Long or noisy lines may require lower transmission speed. The options include [9600], [19200], [38400], [57600] and [115200].
Data Bits
Use this item to set the data transmission size. The options include [7] and [8] (Bits).
Parity
Use this item to select the parity bit. The options include [None], [Even], [Odd], [Mark] and [Space]. A parity bit can be sent with the data bits to detect some transmission errors. Mark and Space Parity do not allow for error detection; they can be used as an additional data bit.
Even: parity bit is 0 if the number of 1's in the data bits is even.
Odd: parity bit is 0 if the number of 1's in the data bits is odd.
Mark: parity bit is always 1.
Stop Bits
The item indicates the end of a serial data packet. The standard setting is [1] Stop Bit. Select [2] Stop Bits for slower devices.
Flow Control
Use this item to set the flow control to prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a "stop" signal can be sent to stop the data flow. Once the buffers are empty, a "start" signal can be sent to restart the flow. Hardware flow uses two wires to send start/stop signals. The options include [None] and [Hardware RTS/CTS].
VT-UTF8 Combo Key Support
Use this item to enable or disable the VT-UTF8 Combo Key Support for ANSI/VT100 terminals.
Recorder Mode
Use this item to enable or disable Recorder Mode to capture terminal data and send it as text messages.
Resolution 100x31
Use this item to enable or disable extended terminal resolution support.
Putty Keypad
Use this item to select Function Key and Keypad on Putty.
Redirection COM Port
Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages.
Resolution
On Legacy OS, the Number of Rows and Columns supported redirection.
Redirection After BIOS POST
If [LoadBooster] is selected, legacy console redirection is disabled before booting to legacy OS. If [Always Enabled] is selected, legacy console redirection is enabled for legacy OS. The default value is [Always Enabled].
Console Redirection
Use this option to enable or disable Console Redirection. If this item is set to Enabled, you can select a COM Port to be used for Console Redirection.
Console Redirection Settings
Use this option to configure Console Redirection Settings, and specify how your computer and the host computer to which you are connected exchange information.
Out-of-Band Mgmt Port
Microsoft Windows Emergency Management Services (EMS) allows for remote management of a Windows Server OS through a serial port.
Terminal Type EMS
Use this item to select the preferred terminal emulation type for out-of-band management. It is recommended to select [VT-UTF8].
Bits Per Second EMS
Use this item to select the serial port transmission speed. The speed used in the host computer and the client computer must be the same. Long or noisy lines may require lower transmission speed. The options include [9600], [19200], [57600] and [115200].
Flow Control EMS
Use this item to set the flow control to prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a "stop" signal can be sent to stop the data flow. Once the buffers are empty, a "start" signal can be sent to restart the flow. Hardware flow uses two wires to send start/stop signals. The options include [None], [Hardware RTS/CTS], and [Software Xon/Xoff].
Data Bits EMS
Statically set to 8.
Parity EMS
Statically set to None.
Stop Bits EMS
Statically set to 1.
Monitor the status of the hardware on your system, including the parameters of the CPU temperature, motherboard temperature, CPU fan speed, chassis fan speed, and the critical voltage.
Enable to activate Trusted Platform Module (TPM) security for your hard disk drives.
This item displays active PCR Banks.
This item displays available PCR Banks.
Use this item to enable or disable SHA256 PCR Bank.
Use this item to enable or disable SHA384 PCR Bank.
Use this item to enable or disable SM3_256 PCR Bank.
Schedule an Operation for the Security Device. NOTE: Your computer will reboot during restart in order to change the State of the Device.
Use this item to enable or disable Platform Hierarchy.
Use this item to enable or disable Storage Hierarchy.
Use this item to enable or disable Endorsement Hierarchy.
Select this item to tell OS to support PPI spec version 1.2 or 1.3. Please note that some HCK tests might not support version 1.3.
Select the Communication Interface to TPM 2.0 Device.
Use this item to select the TPM device to be supported. TPM 1.2 will restrict support to TPM 1.2 devices. TPM 2.0 will restrict support to TPM 2.0 devices. Auto will support both with the default set to TPM 2.0 devices. If TPM 2.0 devices are not found, TPM 1.2 devices will be enumerated.
Displays the Intel ME Subsystem Configuration information as follows:
Operational Firmware Version
ME File System Integrity Value
Use this item to enable or disable UEFI Network Stack.
Use this item to enable or disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.
Use this item to enable or disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.
Use this item to enable or disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.
Use this item to enable or disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.
Use this item to enable or disable the VMD Controller. When enabled, the options below appear.
Use this item to enable or disable VMD Global Mapping.
Use this item to map or unmap Root Port to VMD.
Provides health status for the drivers/controllers.
Instant Flash is a UEFI flash utility embedded in Flash ROM. This utility enables UEFI firmware updates without entering operating systems. To flash UEFI firmware, download and save the new firmware version to bootable USB flash media. Then, using Instant Flash, you can update system firmware directly via Instant Flash menus through the UEFI Menu. The USB flash media must use a FAT32/16/12 file system. When the Instant Flash utility is executed, the utility will show the firmware files on the USB media and their respective information. Select the proper firmware file to update your UEFI, and reboot your system after the UEFI update process is completed.
From this screen, a user may set or change the supervisor/user password for the system. You may also clear the user password.
Set or change the password for the administrator account. Only the administrator has authority to change the settings in the UEFI Setup Utility. Leave it blank and press enter to remove the password.
Set or change the password for the user account. Users are unable to change the settings in the UEFI Setup Utility. Leave it blank and press enter to remove the password.
Use this item to enter the Secure Boot configuration page.
Use this item to enable or disable support for Secure Boot.
Enable to support Windows 8 or later versions Secure Boot.
Expert users can modify Secure Boot Policy variables without full authentication.
Factory Key Provision
Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode.
Install Default Secure Boot Keys
Please install default secure boot keys if it’s the first time you use secure boot.
Clear Secure Boot keys
Force System to Setup Mode - clear all Secure Boot Variables. Change takes effect after reboot.
Export Secure Boot variables
Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device.
Enroll Efi Image
Allow the image to run in Secure Boot mode. Enroll SHA256 Hash certificate of a PE image into Authorized Signature Database (db).
Wait For BMC response for specified time out. In PILOTII, BMC starts at the same time when BIOS starts during AC power ON. It takes around 90 seconds to initialize Host to BMC interfaces.
Use this item to enable or disable FRB-2 timer (POST timer).
Enter value between 1 to 30 minutes for FRB-2 Timer Expiration.
Use this item to configure how the system should respond if the FRB-2 Timer expires. Not available if FRB-2 Timer is disabled.
If enabled, starts a BIOS timer which can only be shut off by Management Software after the OS loads. Helps determine that the OS successfully loaded or follows the OS Boot Watchdog Timer policy.
Change this to enable or disable all features of System Event Logging during boot.
Use this to choose options for erasing SEL.
Use this to choose options for reactions to a full SEL.
Use this item to disable the logging of EFI Status Codes or log only error code or only progress or both.
Use this item to enable or disable PCIe Device Degrade Error Logging Support.
Use this item to enable or disable BMC Out of Band Access.
If [No] is selected, the IP address is assigned by DHCP. If you prefer using a static IP address, toggle to [Yes], and the changes take effect after the system reboots. The default value is [No].
Select to configure BMC network parameters statically or dynamically(by BIOS or BMC). Configuration options: [Static] and [DHCP].
Static
Manually enter the IP Address, Subnet Mask and Gateway Address in the BIOS for BMC LAN channel configuration.
DHCP
IP address, Subnet Mask and Gateway Address are automatically assigned by the network's DHCP server.
VLAN
Enabled/Disabled Virtual Local Area Network. If [Enabled] is selected, configure the items below.
IPV6 Support
Enabled/Disable LAN1 IPV6 Support.
Manual Setting IPMI LAN(IPV6)
Select to configure LAN channel parameters statically or dynamically(by BIOS or BMC). Unspecified option will not modify any BMC network parameters during the BIOS phase.
Select this KCS interface state after POST end. If [Enabled] us selected, the BMC will remain KCS interface after POST stage. If [Disabled] is selected, the BMC will disable KCS interface after POST stage.
This allows you to set the power state after an unexpected AC/power loss. If [Power Off] is selected, the AC/power remains off when the power recovers. If [Power On] is selected, the AC/power resumes and the system starts to boot up when the power recovers. If [Last State] is selected, it will recover to the state before AC/power loss.
Use this item to Load BMC Default Settings.
This allows you to configure the Smbios Event Log Settings. When entering the item, you will see the followings:
Use this item to enable or disable all features of the SMBIOS Event Logging during system boot.
The options include [No], [Yes, Next reset] and [Yes, Every reset]. If Yes is selected, all logged events will be erased.
Use this item to choose options for reactions to a full Smbios Event Log. The options include [Do Nothing] and [Erase Immediately].
Choose option to enable/disable logging of System boot event.
Use this item to enter the increment value for the multiple event counter. The valid range is from 1 to 255.
Use this item to specify the number of minutes which must pass between duplicate log entries which utilize a multiple-event counter. The value ranges from 0 to 99 minutes.
Press to view the Smbios Event Log records.
Display the available boot devices, configuration settings, and boot priority.
Use this item to set the system boot order.
Specifies the Boot Device Priority sequence from available UEFI Hard Disk Drives.
Specifies the Boot Device Priority sequence from available UEFI USB Drives.
Specifies the Boot Device Priority sequence from available UEFI Application.
Fast Boot minimizes your computer's boot time. In fast mode you may not boot from an USB storage device. Ultra Fast mode is only supported by Windows and the VBIOS must support UEFI GOP if you are using an external graphics card. Please notice that Ultra Fast mode will boot so fast that the only way to enter the UEFI System Setup Utility is to Clear CMOS or run the Restart to UEFI utility in Windows.
Configure the number of seconds to wait for the UEFI setup utility.
If this item is set to [On], it will automatically activate the Numeric Lock function after boot-up.
Select whether the Boot Beep should be turned on or off when the system boots up.
Use this item to enable or disable OEM Logo. The default value is [Enabled].
If the computer fails to boot for a number of times the system automatically restores the default settings.
Use this item to configure Boot Failure Guard Count.
When you select this option, the following message “Save configuration changes and exit setup?” will pop-out. Press key or select [Yes] to save the changes and exit the UEFI SETUP UTILITY.
When you select this option, the following message “Discard changes and exit setup?” will pop-out. Press key or select [Yes] to exit the UEFI SETUP UTILITY without saving any changes.
When you select this option, the following message “Discard changes?” will pop-out. Press key or select [Yes] to discard all changes.
Load UEFI default values for all the setup questions. F9 key can be used for this operation.
NVMe Configuration
ACPI Configuration
USB Configuration
Super IO Configuration
Serial Port Console Redirection
H/W Monitor
Trusted Computing
Intel ME Configuration
Network Stack Configuration
VMD Configuration
Driver Health
Instant Flash
ANSI
Extended ASCII character set
ANSI
Extended ASCII character set
VT100
ASCII character set
VT100+
Extended VT100 that supports color and function keys
VT-UTF8
UTF8 encoding is used to map Unicode chars onto 1 or more bytes
VT100
ASCII character set
VT100+
Extended VT100 that supports color and function keys
VT-UTF8
UTF8 encoding is used to map Unicode chars onto 1 or more bytes
07/13/2023
First release of Axial AC101 UEFI manual
